고속 광섬유 레이저 구동기: GaN 레이아웃 설계 실습

고속 광섬유 레이저 구동기: GaN 레이아웃 설계 실습

추상

GaN HEMTs cut gate charge by 5× to 10× and output capacitance by 3× to 5× against silicon, which moves pump driver switching to 500 kHz and beyond. This article gives the overshoot, gate loop, and self-resonance equations at 400 V and 30 A, four layout pain points, and five steps that keep a 1 MHz stage inside its device ratings.

1. 소개

A GaN high-electron-mobility transistor carries 5× to 10× less gate charge, 3× to 5× less output capacitance, and no reverse recovery charge. Those three numbers move a pump driver from 200 kHz to 500 kHz and beyond.

Higher frequency shrinks the passives. A 5 kW pump source that needs 3 L of converter volume at 200 kHz fits near 1 L at 1 MHz, which puts it inside the pump module housing instead of beside it.

The transitions get faster at the same time. Rise and fall times of 1 ns to 5 ns produce dV/dt of 50 V/ns to 200 V/ns, ten to twenty times the silicon rate, so parasitic inductance and capacitance that never mattered now set the waveform.

This article covers the overshoot and gate loop equations, the self-resonance limits of bypass parts, four field pain points, and five layout and component steps built on N4700 Class I ceramic.

2. 핵심 메커니즘

2.1 Switching loss at high frequency

Turn-on loss follows the same product as in silicon, but the transition is far shorter:

P_sw_on = ½ × V_ds × I_d × t_rise × f_sw

where P_sw_on is the turn-on loss, V_ds the drain-source voltage, I_d the switched current, t_rise the rise time, and f_sw the switching frequency. At 400 V, 30 A, a 3 ns rise, and 1 MHz, the loss is 18 W, about what a silicon part shows at 200 kHz. The same loss at five times the frequency buys five times smaller magnetics.

2.2 Parasitic inductance sets the overshoot

At turn-off the loop inductance stores the current that cannot stop instantly:

V_overshoot = L_parasitic × I_d / t_fall

where V_overshoot is the voltage added to the bus, L_parasitic the total loop inductance including the package, the traces, and the capacitor ESL, I_d the switched current, and t_fall the current fall time.

Five nanohenries at 30 A and 2 ns adds 75 V to a 400 V bus, so the device sees 475 V, which is 73% of a 650 V rating. Holding the peak under 80% of rating leaves 120 V of headroom and a loop allowance of 8 nH.

2.3 Gate loop ringing

The gate return inductance and the input capacitance of the device form a series resonant circuit:

f_gate = 1 / (2π × √(L_g × C_iss))

where f_gate is the gate loop ringing frequency, L_g the gate return inductance, and C_iss the input capacitance of the device. To keep ringing above 200 MHz with C_iss = 500 pF, L_g must stay under 1.27 nH, which puts the bypass capacitor within 2 mm of the gate terminals.

Source inductance couples the power loop into the same node. The spike it develops follows:

V_spike = L_source × I_d / t_fall

where V_spike is the gate-source voltage error and L_source the common source inductance. A 0.2 nH shared return at 30 A and 2 ns produces 3 V, which is half the threshold of a 6 V GaN device.

2.4 Self-resonance of the bypass parts

Every capacitor turns inductive above its own self-resonant frequency:

SRF = 1 / (2π × √(ESL × C))

where SRF is the self-resonant frequency, ESL the equivalent series inductance, and C the capacitance. A 100 nF part with 1 nH resonates at 15.9 MHz, and a 10 nF part with 0.3 nH reaches 91.9 MHz.

Above SRF the impedance rises with frequency:

Z_ESL = 2πf × ESL

where Z_ESL is the inductive impedance. A 10 nH capacitor bank holds 12.6 Ω at 200 MHz, which is no longer a bypass. Staged values from 100 nF down to 1 nF keep the band low, even though the self-resonant frequency of a group of identical parts does not move when those parts go in parallel.

Fig. 1 — At 30 A and a 2 ns fall, overshoot rises 15 V per nanohenry, so the 650 V device rating caps the power loop near 8 nH.

3. 엔지니어링 문제점

Pain Point 1: Bypass capacitor ESL triggers the gate

A bypass part with 1 nH to 3 nH of ESL plus the trace inductance gives 2 nH to 5 nH in the gate loop. At 100 V/ns the source inductance couples the power loop current into the gate return.

A 0.2 nH shared return at 30 A and 2 ns adds 3 V to the gate, which is half the threshold of a 6 V device. The resulting false turn-on drives shoot-through current through both switches of a half bridge.

Pain Point 2: A single input capacitor stops working above its resonance

One 10 µF part with 10 nH of ESL presents 12.6 Ω at 200 MHz, so it does nothing for the transient that the 5 ns edge creates. The GaN device then draws its edge current from the loop inductance instead.

The loop answers with the ringing of §2.2, and the LD current feedback path picks up the result as noise on the drive signal.

Pain Point 3: Trace inductance in the power loop

On 2 oz copper over FR-4, a 10 mm trace contributes about 10 nH. A loop that runs from the input capacitor to the drain, through the source, and back past 30 mm of routing carries more inductance than the device package.

Total loop inductance below 2 nH means the whole path fits inside a 5 mm × 5 mm area. That requires a multilayer stack with thin power and ground planes, or a capacitor attached directly to the lead frame.

Pain Point 4: Bypass capacitance that falls with temperature and bias

In a sealed pump module at 60 °C to 75 °C ambient, an X7R bypass capacitor loses 15% to 25% of its capacitance to bias and temperature. The bypass impedance at the switching frequency rises with it.

Ripple then couples into the laser diode current loop, and the 976 nm pump diodes answer with wavelength instability. The effect grows through the thermal cycle, so a bench test at 25 °C does not show it.

4. 설계 단계

Strategy 1: Use Class I dielectric at the gate

A 100 nF N4700 bypass part holds 100 nF at 125 °C under 12 V of bias, against 60 nF to 75 nF for X7R. That difference of 33% to 67% in effective capacitance lowers the gate loop impedance by the same ratio.

Zero DC bias loss and a ±30 ppm/°C coefficient complete the job: the gate impedance stays at its design value from −55 °C to +125 °C, so the false-trigger margin of Pain Point 1 holds across the temperature range.

Strategy 2: Stage the decoupling values

Self-resonance falls as √(ESL × C), so a small part with low ESL covers a higher band. A 100 nF N4700 part with 1 nH self-resonates at 15.9 MHz, and an 0402 10 nF part at 0.3 nH reaches 91.9 MHz.

Place 10 to 20 small parts of 10 nF to 47 nF in a ring around the device, within 3 mm of the drain terminal, and add one 100 nF part for the lower band. Stages at 100 nF, 10 nF, and 1 nF give low impedance from 1 MHz to past 200 MHz. Paralleling identical parts lowers the impedance and leaves their common self-resonant frequency where it was, so the values must differ.

Strategy 3: Build the power loop into the board stack

Put a 0.1 mm dielectric between the power plane and the ground plane. That layer gives about 30 pF/cm², so 1 cm² of overlap carries 300 pF with inductance below 0.1 nH.

The embedded plane serves the transient currents above 100 MHz that no discrete part reaches, and it shortens the physical loop at the same time. Add HVCT8G parts at the bus entry for the 1 MHz to 10 MHz band, where the planes are too small to store the energy.

Strategy 4: Return the gate driver on a Kelvin source

Route the gate driver return on its own trace to the source terminal, separate from the power current path, so the power loop does not induce voltage in the gate loop.

Run that trace on an inner layer with a ground shield on both sides and hold its inductance below 0.5 nH. The measured gate waveform then shows the 200 MHz ringing of §2.3, and the 3 V spike leaves the gate-source path.

Strategy 5: Rate the voltage at 2× and confirm the loop on the first article

Use 1 kV parts on a 400 V bus. The margin covers the overshoot of §2.2 and keeps the peak below the partial discharge inception voltage, so the bypass capacitance does not drift over the service life. A 필름 콘덴서 at the DC input and a 고속회복 다이오드 clamp cover the energy that the plane capacitance cannot absorb.

Measure the switch node on the first article with a low-inductance probe and a coaxial shunt. A current probe confirms the loop inductance from the ring frequency, which is the only way to verify an 8 nH loop before production.

구성 요소 매개변수	전형적인 가치	시험 조건
정격 전압(HVCT8G 시리즈)	10 kV DC	60초 동안 1.5배속으로 고전압 가열
정전 용량	4700 pF ±20% (472M)	1MHz, 1V rms
1MHz에서의 ESR	50mΩ 미만	-
루프 인덕턴스(E40 코드)	8nH 이하	단자 간격 40mm
절연 저항	500V DC에서 10GΩ 이상	25°C, 상대습도 60%
온도 범위	−40°C ~ +125°C	IEC 60068-2 시리즈
펄스 dv/dt 기능	50kV/µs 이상	정격 전압에서

5. HVC N4700 capacitors for GaN pump drivers

Three requirements drive this node: a bypass capacitance that does not move with bias or temperature, low loss at the switching harmonics, and package inductance low enough for the gate loop. HVC builds N4700 (T3M) Class I parts on a SrTiO3 base for that set, in a 6,000 m² owned factory in Dongguan, from 1 kV to 100 kV.

여기서 중요한 6가지 매개변수

• No DC bias capacitance loss. Class I dielectric holds nominal capacitance at any bias, so the gate bypass stays at 100 nF where an X7R part falls 20% to 50% and loses the false-trigger margin.
• Temperature coefficient of ±30 ppm/°C. Capacitance stays within ±0.35% from −55 °C to +125 °C, against ±15% for X7R, so bypass impedance holds in a module that runs at 70 °C to 85 °C.
• tan δ of 0.1% or lower. On a 100 nF bypass part at 200 MHz and 10 V AC the dielectric loss falls to 6.3 mW against 63 mW for an X7R part at 2%, which removes a thermal runaway path.
• Package inductance below 30 nH in the radial-lead HVCT8G outline, with the small-case parts well under 1 nH, so a staged array covers 1 MHz to beyond 200 MHz.
• No aging drift. Capacitance stays within 2% after 50,000 h at 85 °C, with intrinsic life beyond 100,000 h, so bypass performance does not decay into intermittent false triggering.
• Qualified as a drop-in for first-tier brands in field-repair programmes and specified by laser OEMs in new high-speed platforms. HVC parts match the electrical parameters and package dimensions of Murata 나사형 및 방사형 리드 고전압 부품.

배송 및 지원

Standard parts ship in 4–8 weeks, and matched custom sets in 6–10 weeks. HVC applications engineering supports gate loop analysis, decoupling array design for wideband impedance, layout review for minimum loop inductance, and custom voltage and capacitance combinations.

Send the bus voltage, switched current, fall time, device capacitance values, and the target overshoot. HVC returns a decoupling plan with part numbers, ESL and SRF values, and a two-sample evaluation kit within five working days.

6. 자주 묻는 질문

Q1: How much overshoot does GaN layout inductance create?

V_overshoot = L_parasitic × I_d / t_fall. At 30 A with a 2 ns fall, every nanohenry adds 15 V, so 5 nH adds 75 V to a 400 V bus and the device sees 475 V, which is 73% of a 650 V rating. Holding the peak below 80% of rating sets an 8 nH loop limit.

Q2: Why does a single 10 µF input capacitor fail at 1 MHz?

Because its ESL dominates above self-resonance. A 10 µF part with 10 nH holds 12.6 Ω at 200 MHz, so it cannot supply a 5 ns edge. Use a staged array of 10 nF to 100 nF parts within 3 mm of the drain, plus embedded plane capacitance for the band above 100 MHz.

Q3: Does putting capacitors in parallel raise the self-resonant frequency?

No. Paralleling identical parts divides ESL and multiplies capacitance by the same ratio, so SRF = 1 / (2π × √(ESL × C)) stays where it was. The impedance magnitude falls, and the values must differ to extend the band. A 100 nF part with 1 nH resonates at 15.9 MHz and an 0402 10 nF part at 0.3 nH reaches 91.9 MHz.

Q4: How close must the gate bypass capacitor sit?

Within 2 mm of the gate-source terminals. With C_iss of 500 pF, ringing above 200 MHz needs gate loop inductance below 1.27 nH, and 2 mm of layout is most of that allowance. Return the driver on a Kelvin source trace and hold its inductance below 0.5 nH.

Q5: What causes gate false triggering at 100 V/ns?

Common source inductance. V_spike = L_source × I_d / t_fall, so a 0.2 nH shared return at 30 A and 2 ns puts 3 V on the gate, which is half the threshold of a 6 V part. The spike is also a shoot-through risk in a half bridge, since both devices conduct at once.

Q6: Why does X7R bypass capacitance shrink in the enclosure?

Class II ceramic loses 15% to 25% of its capacitance to DC bias and temperature at 60 °C to 75 °C ambient. Bypass impedance rises with that loss, ripple couples into the diode current path, and the 976 nm pump wavelength drifts. Class I N4700 holds nominal capacitance and ±0.35% over the full range.

7. 참조

1. E. 쿠펠, WS 쟁글, J. 쿠펠, 고전압 공학 기초, 제2판, 뉴네스, 2000.
2. N. 모한, TM 언델랜드, WP 로빈스, 전력 전자공학: 컨버터, 응용 분야 및 설계, 3판, Wiley, 2003.
3. MIL-HDBK-217F 공지 2, 전자 장비의 신뢰성 예측, 1995.
4. IEC 60384-1:2018, 전자 장비용 고정 콘덴서 — 1부: 일반 사양.
5. 미래를 위한 에너지: 고전압 MLCC가 현대 전자 제품의 효율성을 높이는 방법무라타, https://www.murata.com/en-eu/s/blog/powering-the-future-how-high-voltage-mlccs-drive-efficiency-in-modern-electronics.html .
6. Infineon FF300R17KE4P 보호를 위한 스너버 회로 권장 사항 요청, 인피니언 개발자 커뮤니티, https://community.infineon.com/t5/IGBT/Request-for-Snubber-Circuit-Recommendation-for-Protecting-Infineon-FF300R17KE4P/td-p/1241451 .
7. D. Li, Y. Zhong, X. Zhou 및 G. Zhai, 위상장을 이용한 다층 세라믹 커패시터 파괴 분석 방법, IEEE 부품, 포장 및 제조 기술 거래, 제14권, 제2호, 2024년, 211-220쪽. https://doi.org/10.1109/tcpmt.2024.3359598.
8. GB/T 6346.1-2024, 电子设备用固定电容器 第1 부분 : 总规范 (전자 장비에 사용되는 고정 커패시터 – 파트 1: 일반 사양). 베이징: 國家市场监督管理总局, 2024.
9. 미국 8,570,711, 다층 세라믹 전자 부품 (1–5 kV MLCC용 아크 방전 억제), 삼성전자, 2013년 특허 등록, https://www.freepatentsonline.com/8570711.html .
10. HVC 애플리케이션 엔지니어링 팀, 고전압 세라믹 커패시터 기술 자료, https://www.hv-caps.com