PFN Energy Storage Volume Reduction in Plasma Igniters

PFN Energy Storage Volume Reduction in Plasma Igniters

추상

A pulse-forming network holds the ignition charge and releases it with the waveform the torch needs, and it occupies volume that portable cutters and robot-mounted torches do not have. This article gives the energy-density equations, the dielectric comparison that removes 56 % of the active volume, the inductance and rise-time constraint, four miniaturization traps, six design steps and the thermal arithmetic.

1. 소개

Every plasma cutting igniter carries a pulse-forming network: the energy storage and shaping unit that holds the charge for the ignition pulse and releases it with the waveform the torch needs.

Traditional networks use wound film capacitors, chunky inductors and generous spacing for creepage. Together they take a large share of the enclosure, and the market is moving toward compact machines that mount the torch directly on a robot arm.

The engineering tension is real. Pulse energy follows E = ½CV², so shrinking the capacitor at constant energy needs either a higher voltage, which complicates insulation and creepage, or a higher energy density in the dielectric.

This article gives the energy-density arithmetic, the dielectric comparison, the inductance constraint that keeps the pulse shape, the thermal limit that decides how small the part can get, and the six steps that hold pulse fidelity at reduced volume.

2. 핵심 메커니즘

2.1 Energy in the dielectric

The network stores ignition energy as electrostatic field energy, and the field energy depends on the dielectric and the volume it occupies.

E = ½ ε₀ ε_r E_max² V_diel

where E is the stored energy in joules, ε₀ stands for the permittivity of free space, 8.854 × 10⁻¹² F/m, ε_r is the relative permittivity, E_max is the peak electric field in volts per metre, and V_diel covers the active dielectric volume in cubic metres. Two levers follow: raise the permittivity, or raise the field the dielectric tolerates.

2.2 Energy density and the dielectric comparison

Dividing by volume gives the number that decides how much space a given pulse energy needs.

w = E / V_diel = ½ ε₀ ε_r E_max²

where w is the volumetric energy density in joules per cubic metre. A SrTiO3 Class I dielectric at ε_r = 2000 and 10 MV/m reaches 0.885 J/cm³, and a BOPP film at ε_r = 2.2 and 200 MV/m reaches 0.390 J/cm³. For the 235 mJ that a 4.7 nF tank holds at 10 kV, the ceramic needs 0.27 cm³ of active dielectric and the film needs 0.60 cm³, so the ceramic removes 56 % of the active volume.

The comparison holds only at the rated field. A high-permittivity Class II ceramic collapses under DC bias, losing 30–70 % of its rated capacitance at rated voltage, which erases the volume advantage and distorts the pulse envelope at the same time.

2.3 Pulse shape and the inductance floor

Pulse fidelity depends on the loop inductance and the capacitance together, because they set the rise time.

t_r ≈ 2.2 √(L C)

where t_r is the 10–90 % rise time of the pulse, L is the total loop inductance, and C is the network capacitance. The rise time also has a floor set by the part itself: a capacitor rated above 50 kV/µs at 10 kV needs at least 200 ns to reach rated voltage, and a design margin of two puts the target at 400 ns.

Solving the rise relation for that target with a 4.7 nF capacitor gives a loop inductance of 7.0 µH, which is series inductance that the design adds. The parasitic part of the loop, meaning the capacitor ESL plus the interconnect, then has to stay small against it. A 2 % allowance sets a parasitic limit of 140 nH, and the resulting loop presents 38.7 Ω of characteristic impedance and 259 A of peak current at 25 kV/µs.

2.4 The thermal limit on small bodies

Every ignition event loses a fraction of the stored energy in the dielectric, and the loss per resonant cycle follows the loss factor.

E_loss = 2π tanδ E

where E_loss is the energy lost per cycle, tanδ is the loss factor, and E is the stored energy. A Class I part at tanδ = 0.1 % loses 1.48 mJ per event out of 235 mJ, and a Class II part at 2 % loses 29.5 mJ.

ΔT = P_loss R_th

where ΔT is the body temperature rise, P_loss is the average dissipation, and R_th is the thermal resistance from the body to the surroundings. At 100 events per second and 60 K/W, the Class I part runs 8.9 K above ambient and the Class II part runs 177 K above it. Shrinking the body raises R_th, so volume reduction and loss reduction belong in the same decision.

Fig. 1 — The same 235 mJ of ignition energy needs 0.60 cm³ of BOPP film dielectric and 0.27 cm³ of SrTiO3 Class I dielectric.

3. 엔지니어링 문제점

Pain Point 1: Capacitance collapse under DC bias

Compact Class II ceramics lose 30–70 % of their rated capacitance at rated DC voltage. The network then holds far less energy than the label promises, designers oversize the capacitor to compensate, and the miniaturization gain disappears along with the accuracy of the pulse math.

Pain Point 2: Parasitic inductance growth from cramming

When capacitors, busbars and switches are packed together the current loop is often routed around other parts, which adds 50–150 nH. The rise time stretches, the overshoot changes, and the ignition timing moves away from the design point.

Pain Point 3: Thermal concentration in a small body

A small body with high stored energy concentrates loss into little mass and a higher thermal resistance. The body temperature rises, loss rises further in any lossy dielectric, and the failure arrives weeks after installation with no external warning.

Pain Point 4: Creepage and partial discharge in tight spaces

Shrinking the network shrinks the creepage between high-voltage nodes, and partial discharge starts at 60–80 % of rated voltage once the spacing drops below the design value. Sustained discharge erodes the insulation, and the eventual failure is unpredictable.

4. 설계 단계

Strategy 1: Choose the dielectric on energy density at the rated field

Compare candidate materials on w = ½ε₀ε_r E_max² at the field the part actually holds, and verify the capacitance at rated DC bias and at the operating temperature. A datasheet value taken at zero bias says nothing about either.

Strategy 2: Set the inductance allowance on the parasitic part

Fix the series inductance from the required rise time, then allow at most 2 % of it for capacitor ESL and interconnect. For a 7.0 µH loop that means 140 nH, which is a layout specification and not a component specification.

Strategy 3: Design the thermal path with the electrical one

Provide a low-resistance thermal path from the capacitor bodies to the enclosure or a spreader plate, and confirm from the measured loss per pulse that the steady-state body temperature stays below the derating point of the dielectric.

Strategy 4: Verify partial discharge in the compacted assembly

Test the finished network at 120 % of the maximum ignition voltage inside the real enclosure, and require PD below 5 pC per component. Creepage that works on the bench can fail once the potting compound and the enclosure are in place.

Strategy 5: Simulate the envelope on extracted parasitics

Build a model with the measured C, ESL and ESR of every component plus the extracted loop inductance, and confirm the rise time and the overshoot stay inside the ignition window before any hardware is cut. A 필름 콘덴서 choice changes both terms at once.

Strategy 6: Build a modular cell from parallel capacitors

Assemble the energy unit from smaller parallel parts instead of one large part. Thermal distribution improves, the parallel paths lower ESL, and the same cell can be scaled from a portable machine to a heavy-plate system.

구성 요소 매개변수	전형적인 가치	시험 조건
정격 전압(HVCT8G 시리즈)	10 kV DC	60초 동안 1.5배속으로 고전압 가열
정전 용량	4700 pF ±20% (472M)	1MHz, 1V rms
1MHz에서의 ESR	50mΩ 미만	25 ° C
루프 인덕턴스(E40 코드)	8nH 이하	단자 간격 40mm
절연 저항	500V DC에서 10GΩ 이상	25°C, 상대습도 60%
온도 범위	−40°C ~ +125°C	IEC 60068-2 시리즈
펄스 dv/dt 기능	50kV/µs 이상	정격 전압에서

5. HVC capacitors for compact pulse-forming networks

Three properties decide how much volume a network can shed: energy density at the rated field, loss per pulse and parasitic inductance. HVC builds N4700 parts for all three.

여기서 중요한 6가지 매개변수

• A SrTiO3 Class I dielectric at ε_r 2000 delivers high energy density at the rated bias without the collapse that Class II materials show.
• tanδ at or below 0.1 % holds the loss per event at 1.48 mJ out of 235 mJ, so a small body stays inside its thermal limit at 100 events per second.
• ±30 ppm/°C holds capacitance steady, so the network's impedance and rise time do not drift with warm-up or duty cycle.
• PD below 5 pC supports aggressive creepage reduction, because the dielectric itself does not discharge at compact spacings.
• The HVCT8G screw-terminal and radial-lead packages keep internal paths short, which holds the parasitic inductance inside the 140 nH allowance.
• 현장 사례: HVC 40kV/441 스크류 타입 커패시터가 고전압 현장 서비스 프로그램에서 국제 표준 부품을 대체했으며, 동일한 구조로 전기적 매개변수가 일치합니다. 상호 참조 후보자.

배송 및 지원

표준 부품은 4~8주, 매칭 스택은 6~10주 내에 배송됩니다. 1kV 이상에서는 매칭 스택을 포함한 직렬 구성으로 이용 가능합니다. 저항기 등급 그리고 클램핑 고속회복 다이오드.

Send the required pulse energy, rise time, repetition rate and enclosure volume. HVC returns a network capacitor recommendation with measured energy density, ESL, ESR and PD data for that operating point.

6. 자주 묻는 질문

Q1: What sets the energy density of a capacitor dielectric?

w = ½ε₀ε_r E_max². Permittivity and permissible field both enter, so a material with high ε_r at a modest field can beat one with low ε_r at a high field.

Q2: How much volume does a Class I ceramic save over film?

For 235 mJ at 10 kV, a SrTiO3 Class I part needs 0.27 cm³ of active dielectric against 0.60 cm³ for BOPP film at 200 MV/m, which is 56 % less.

Q3: Can a smaller network simply use a higher field?

Up to the partial-discharge limit. Discharge starts at 60–80 % of rated voltage once creepage drops below the design value, so the field and the spacing have to be designed together.

Q4: How much inductance is allowed in the loop?

Whatever the rise time needs, plus 2 % for parasitics. A 400 ns rise with 4.7 nF needs 7.0 µH of series inductance, which allows 140 nH of capacitor ESL and interconnect.

Q5: Why does the part heat up in a small body?

Loss per cycle runs at 2π tanδ times the stored energy, and a small body has both less mass and a higher thermal resistance. At 100 events per second the difference between 0.1 % and 2 % loss is 8.9 K against 177 K.

Q6: Why build the cell from parallel capacitors?

Parallel parts spread the heat, lower the effective ESL, and let one cell design scale from a portable cutter to a heavy-plate machine without a new qualification.

7. 참조

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2. N. 모한, TM 언델랜드, WP 로빈스, 전력 전자공학: 컨버터, 응용 분야 및 설계, 3판, Wiley, 2003.
3. MIL-HDBK-217F 공지 2, 전자 장비의 신뢰성 예측, 1995.
4. IEC 60384-1:2021, 전자 장비용 고정 콘덴서 - 1부: 일반 사양, 제6판. 제네바: IEC, 2021.
5. IEC 61071:2017, 전력 전자 장치용 커패시터, 제2판. 제네바: IEC, 2017.
6. GB/T 17702-2021, 电력电子电容器. 북경: 中國标准会版社, 2021.
7. Y. Zhou, B. Chen, C. Tian, ​​J. Yuan 및 Y. Chen, 전기 장비의 내전압 시험 및 부분 방전 측정을 위한 병렬 다이오드 클램프형 선형 변환기, High Voltage, vol. 8, no. 1, pp. 171-182, 2023. https://doi.org/10.1049/hve2.12312.
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11. HVC 애플리케이션 엔지니어링 팀, 고전압 세라믹 커패시터 기술 자료, https://www.hv-caps.com