Magnetic Pulse Compression Design for Plasma Ignition Modules

Magnetic Pulse Compression Design for Plasma Ignition Modules

추상

Thick and coated plate needs an ignition pulse that combines high voltage, high current and a fast edge, and a semiconductor switch alone handles that duty badly. This article gives the saturable-core equations, the compression ratio arithmetic, a three-stage chain worked through in numbers, four design pain points, six implementation steps and the instrumentation that shows the chain working.

1. 소개

Striking an arc on thick, coated or highly conductive plate needs an ignition pulse with high peak voltage, high peak current and a fast edge at the same time. The practical way to build one is to compress stored energy in time.

Charge a capacitor slowly, then release it in a few hundred nanoseconds through the ignition transformer. A semiconductor switch struggles with that duty, because fast current risetimes force either very large devices or damaging snubber losses.

Magnetic pulse compression uses a chain of saturable inductors. Each one is passive, robust and lossless until the moment its core saturates, when it switches from high impedance to low impedance and transfers the energy downstream.

This article gives the core physics, the compression arithmetic worked through a three-stage chain, four pain points, six implementation steps, and the capacitor properties that make the stage time constants predictable.

2. 핵심 메커니즘

2.1 The charge interval

A compression stage holds a storage capacitor, a saturable inductor and the next stage's capacitor. During the charge interval the core sits unsaturated and presents a large inductance.

t_charge = π √(L_unsat C_n)

where t_charge is the charge interval in seconds, L_unsat is the unsaturated inductance of the saturable inductor, and C_n is the storage capacitance of stage n. A 100 µs charge interval into a 4.7 nF capacitor needs 216 mH of unsaturated inductance.

2.2 The compression ratio

When the capacitor voltage reaches its design value the core saturates, the inductance collapses, and the energy transfers into the next capacitor in a fraction of the charge time.

CR = t_charge / t_discharge = √(L_unsat / L_sat)

where CR is the compression ratio of the stage, t_discharge is the transfer interval, and L_sat is the saturated inductance. The ratio follows directly from the inductance swing, so a core that saturates to 1 % of its unsaturated value gives CR = 10, one that saturates to 3 % gives CR = 5.8, and a ratio of 15 requires the inductance to fall to 0.44 %.

2.3 Core sizing from the volt-second product

The core cross-section comes from Faraday's law integrated over the charge interval.

∫ V(t) dt = N A_core ΔB_sat

where the integral is the volt-second product of the charging waveform, N is the number of turns, A_core is the core cross-sectional area, and ΔB_sat is the usable flux swing. A 10 kV stage charged over 100 µs presents 1 V·s, so the core area and the turns count come from the capacitance and the charge time, and no steady-state current rating enters the calculation.

2.4 The chain and the impedance ladder

A chain of m stages multiplies the individual ratios, and the capacitance falls by one factor of CR at every step.

t_final = t_initial / (CR₁ CR₂ … CR_m)

where t_final is the output pulse width, t_initial is the charge interval of the first stage, and CR₁ through CR_m are the stage ratios. Three stages at CR = 10 turn a 100 µs charge into a 100 ns discharge.

Holding the energy constant across the chain sets the rest of the ladder. The capacitance falls by 10 per stage, so the voltage rises by √10, and the peak current rises by √10, while the characteristic impedance stays fixed because the saturated inductance falls in step with the capacitance.

E = ½ C V²

where E is the stored energy, C is the stage capacitance, and V is the stage voltage. The 235 mJ stored in stage 1 at 10 kV appears unchanged at 47 pF and 100 kV in stage 3, where the saturated inductance is 21.6 µH and the characteristic impedance is still 678 Ω. The stage current rises from 14.7 A to 147 A across the chain.

Fig. 1 — Three compression stages at CR = 10 turn a 100 µs charge into a 100 ns discharge while the 235 mJ of stored energy stays constant.

3. 엔지니어링 문제점

Pain Point 1: Core reset and remnant flux

After each pulse the core must return to a defined negative flux level, or the next pulse starts from an unknown point and the compression ratio drifts. A design without a reset winding, or one using a core material with low squareness, shows pulse-to-pulse jitter that appears as ignition timing scatter.

Pain Point 2: Capacitor ESL judged against the wrong inductance

The 8 nH of a screw-terminal capacitor looks significant against a saturated inductance of a few microhenries. In a first stage with 2.16 mH of saturated inductance it adds 0.0004 %, and even in the 21.6 µH final stage it adds 0.04 %. The interconnect, not the capacitor, is the term worth controlling, and the layout is where the compression ratio is actually lost.

Pain Point 3: Loss accumulation at high repetition rate

Core hysteresis, eddy currents and capacitor loss all scale with frequency and flux swing. Above a few hundred hertz the chain heats, the saturation flux density of the core falls with temperature, and the compression ratio degrades without any change to the circuit.

Pain Point 4: Voltage grading across the magnetic switch

Each stage sees a transient close to the full stage voltage. Uneven distribution across turns or across core layers starts partial discharge, and sustained discharge destroys the core insulation over time. The stage then stops compressing altogether, and the failure arrives with no visible external damage.

4. 설계 단계

Strategy 1: Model the chain with the interconnect inductance included

Extract the ESL of every storage capacitor and the inductance of every connection, then check what the extra inductance does to the final stage. In a 21.6 µH stage a 500 nH connection adds 2.3 % to the saturated inductance and costs about 1 % of the compression ratio, so the allowance belongs to the wiring.

Strategy 2: Design the reset circuit explicitly

Use a reset winding with a controlled current, or a resistor-diode reset, to return the core flux to a fixed negative level before every event. Verify the reset current in the pre-fire sequence, and do not take the schematic's word for it.

Strategy 3: Match the core to the repetition rate

Choose nanocrystalline tape for low eddy loss, derate the saturation flux density by 10 % at the maximum module temperature, and characterize the B-H loop at the operating frequency and temperature before freezing the design.

Strategy 4: Grade the voltage and manage the insulation

Use segmented windings with equal voltage per layer, encapsulate the core assembly in void-free resin, and verify partial discharge at 120 % of the maximum stage voltage. Target the same 5 pC floor that the capacitors in the chain meet.

Strategy 5: Instrument the chain

Fit a fast voltage probe at each stage capacitor and a Rogowski coil at the final stage, and log the compression ratio per ignition event. Alarm when the ratio drops below 80 % of nominal, which is the earliest symptom of core or capacitor aging.

Strategy 6: Pair the chain with low-ESL storage capacitors

지정 N4700 (T3M) Class I parts: a SrTiO3 dielectric with tanδ at or below 0.1 %, a temperature coefficient of ±30 ppm/°C, 1 kV to 100 kV ratings and PD below 5 pC. A compact body keeps both ESR and ESL low, and a 필름 콘덴서 with a higher loss factor and a larger loop works against the final stage.

구성 요소 매개변수	전형적인 가치	시험 조건
정격 전압(HVCT8G 시리즈)	10 kV DC	60초 동안 1.5배속으로 고전압 가열
정전 용량	4700 pF ±20% (472M)	1MHz, 1V rms
1MHz에서의 ESR	50mΩ 미만	25 ° C
루프 인덕턴스(E40 코드)	8nH 이하	단자 간격 40mm
절연 저항	500V DC에서 10GΩ 이상	25°C, 상대습도 60%
온도 범위	−40°C ~ +125°C	IEC 60068-2 시리즈
펄스 dv/dt 기능	50kV/µs 이상	정격 전압에서

5. HVC capacitors for compression chains

Three properties keep a stage time constant predictable: low ESR, low ESL and a stable capacitance across temperature and pulse count. HVC builds N4700 parts for all three.

여기서 중요한 6가지 매개변수

• tanδ at or below 0.1 % keeps the stage loss small, so the chain does not heat its own cores and shift the compression ratio.
• ±30 ppm/°C holds the stage capacitance, and therefore the charge interval, steady from the first pulse of a shift to the last.
• PD below 5 pC keeps the storage capacitors from becoming discharge sources inside a sealed, voltage-stressed chain.
• 1 kV to 100 kV ratings match the per-stage voltage of compact pilot igniters through multi-stage main-arc injectors.
• The HVCT8G screw-terminal cylindrical package carries the final stage's peak current without lead cracking or dielectric fatigue.
• 현장 사례: HVC 40kV/441 스크류 타입 커패시터가 고전압 현장 서비스 프로그램에서 국제 표준 부품을 대체했으며, 동일한 구조로 전기적 매개변수가 일치합니다. 상호 참조 후보자.

배송 및 지원

표준 부품은 4~8주, 매칭 스택은 6~10주 내에 배송됩니다. 1kV 이상에서는 매칭 스택을 포함한 직렬 구성으로 이용 가능합니다. 저항기 등급 for the stage divider.

Send the required final pulse width, peak current, tank voltage and repetition rate. HVC returns a stage-by-stage capacitor recommendation with ESL and ESR data plus core sizing guidance for the inductance ladder.

6. 자주 묻는 질문

Q1: How is the compression ratio of one stage defined?

As the square root of the inductance swing. CR = √(L_unsat/L_sat), so a core that saturates to 1 % of its unsaturated inductance gives CR = 10, and 3 % gives CR = 5.8.

Q2: How large is a three-stage compression chain?

It depends on the pulse width, not on the energy. Three stages at CR = 10 take a 100 µs charge to 100 ns, with stage capacitances of 4.7 nF, 470 pF and 47 pF at 10 kV, 31.6 kV and 100 kV.

Q3: Does the capacitor ESL limit the compression?

Barely. Eight nanohenries against the 21.6 µH of a final stage adds 0.04 %. The wiring between stages carries hundreds of nanohenries and is the term worth controlling.

Q4: What sets the core cross-section?

The volt-second product. ∫V dt must equal N A_core ΔB_sat over the charge interval, so a 10 kV stage charged for 100 µs presents 1 V·s and the core area follows from that.

Q5: Why does the compression ratio drift at high repetition rate?

Core loss heats the tape, and saturation flux density falls with temperature. Derate ΔB_sat by 10 % at the maximum module temperature and characterize the B-H loop at the real operating frequency.

Q6: How do I know the chain is aging?

Log the compression ratio per event with a fast probe on each stage capacitor and a Rogowski coil at the output. A ratio below 80 % of nominal is the earliest sign of core or capacitor degradation.

7. 참조

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2. N. 모한, TM 언델랜드, WP 로빈스, 전력 전자공학: 컨버터, 응용 분야 및 설계, 3판, Wiley, 2003.
3. MIL-HDBK-217F 공지 2, 전자 장비의 신뢰성 예측, 1995.
4. IEC 60384-1:2021, 전자 장비용 고정 콘덴서 - 1부: 일반 사양, 제6판. 제네바: IEC, 2021.
5. IEC 61071:2017, 전력 전자 장치용 커패시터, 제2판. 제네바: IEC, 2017.
6. ГОСТ IEC 61071-2014, Kondensatorы silовые электронные (전력전자용 커패시터). 모스크바: 스탠다르틴포름, 2014.
7. H. Liu 외, BOPP 필름 커패시터의 부분 방전 거동에 대한 전자기장의 영향IEEE 유전체 및 전기 절연 거래(IEEE Transactions on Dielectrics and Electrical Insulation), 제30권, 제6호, 2617-2624쪽, 2023. https://doi.org/10.1109/tdei.2023.3304600
8. P. 모르슈이스와 M. 예로넨세, HVDC 케이블 절연체의 공간 전하, IEEE 1997 전기 절연 및 유전 현상 연례 보고서 컨퍼런스, pp. 28-31, 1997. https://doi.org/10.1109/ceidp.1997.634551.
9. AN2001_06 — IGBT의 직렬 연결, Infineon Technologies, AN2001_06, http://www.infineon.com/dgdl/Infineon-AN2001_06_Series_connection_of_IGBTs-AN-v1.0-en.pdf?fileId=db3a304412b407950112b40f000d12f7 .
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11. HVC 애플리케이션 엔지니어링 팀, 고전압 세라믹 커패시터 기술 자료, https://www.hv-caps.com